Samsung announces new 3D stacked chip package

Ever the innovator, Samsung have developed an enhanced 3D stacked chip package that the company says boosts performance without sacrificing space requirements. You can expect to see these 3D chips in Samsung NAND Flash packaging beginning next year.

Samsung engineers have found a way to get around the traditional barrier to stacking: wire-bonding. In the new 3D chip packages, Samsung will reveal a stack of circuits that are connected directly, not using the wire-bonding that is so prevalent in today’s chips. According to the company, the savings are definitely noticeable: 30 percent thinner on average in terms of physical space and 15 percent less on average in terms of footprint.

For the record, the name of the new technology is WSP, which stands for wafer-level processed stack package. Look for it in 2007 in the iPod Nano-er.