IBM today announced that its scientists have achieved two major milestones that could enable the IT industry to produce higher performing, lower power devices as early as several years from now.
IBM has developed the first transistor using strained silicon directly on insulator (SSDOI) technology that provides high performance while eliminating manufacturing problems. Also, IBM is the first to combine two different underlying silicon layers that simultaneously maximize the performance of the key transistors used in complementary metal oxide semiconductor (CMOS) devices, which are the foundation for everything from cell phones to PCs to supercomputers.
CMOS technology, a high performance, low-power chip, has been widely used in electronic devices because it’s been scaleable on a path following Moore’s Law the past three decades. However, continuing this CMOS performance trend has become extremely difficult because the industry is approaching the fundamental physical limits of CMOS scaling.
The industry is now aggressively seeking new ways to make electric charges move faster through device channels because doing so increases circuit speeds and reduces power consumption. Strained silicon technology provides high electron mobility by stretching the top silicon layer with an underlying layer of silicon germanium (SiGe). IBM has previously reported a 20-30 % performance enhancement using strained silicon.
However, the presence of a SiGe layer causes material and process integration challenges. IBM is the first to fabricate transistors using ultra-thin SSDOI structures that bypass this SiGe layer, thereby providing high electron mobility while eliminating material and process integration problems.
Another way to improve CMOS performance is to increase the mobility of its positive charges, or holes, through the device channels. IBM has been able to integrate devices with 2.5 times higher hole mobility into conventional CMOS technology by combining two substrates in the same wafer. This resulted in a 40-65% performance enhancement.
“These two innovative techniques are relatively simple to implement using standard wafer processing techniques,” said Dr. T. C. Chen, VP Science and Technology, IBM Research. “Implementing either could provide the industry with higher performing and lower power chips; combining the techniques could generate even higher performance and lower power.”
How IBM Created the First Transistor with Strained Silicon Directly on Insulator Technology
The SSDOI structure was created by transferring strained Si grown epitaxially, or layer by layer, on relaxed SiGe to a buried oxide layer. The SiGe layer was removed before fabricating the device. Strain retention was confirmed in the strained Si layer after the layer transfer process and thermal cycles. Electron and hole mobility enhancements were confirmed in MOSFETs fabricated on SSDOI. Fabrication of Sub-60 nm FETs were also demonstrated on SSDOI.
The Benefits of CMOS Fabrication on Hybrid Substrate
CMOS is made of two types of transistors: positively-charged field effect transistors (PFETs), and negatively charged FETs (NFETs). For PFETs, hole mobility is known to be 2.5 times higher on (110) surface-orientation compared to that on standard wafer with (100) surface-orientation. IBM has created a hybrid-orientation technology (HOT) where CMOS is fabricated on hybrid substrate with different crystal orientations to achieve significant PFET performance enhancement. In the HOT technology, layer transfer process, block-level trench etch, and epitaxial regrowth were performed before conventional CMOS device process. An enhancement of 40-65% for the PFET was demonstrated on a 90 nm node CMOS technology.
IBM will present details of the innovative techniques in two papers, titled “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs” and “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations” at the International Electron Devices Meeting (IEDM) held in Washington, D.C. from December 7-10, 2003. This project was a collaboration between researchers and developers at the IBM Semiconductor Research and Development Center, IBM Research and IBM Microelectronics Division.