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ARM Unveils New Mobile Technology

ARM the industry’s leading provider of 16/32-bit embedded RISC processor solutions, today announced at the Embedded Processor Forum in San Jose, Calif., the launch of the ARM11™ microarchitecture, designed to address the needs of next-generation wireless and consumer devices. The ARM11 microarchitecture targets a performance range of 400 to 1,200 Dhrystone MIPS, while meeting the low power needs and cost requirements of battery-powered and high-density embedded applications.

The ARM11 microarchitecture is the first implementation of the ARMv6 instruction set architecture (ARM Announces Technical Details of Next-Generation Architecture — Oct. 17, 2001), and is designed to address the requirements of embedded applications processors, advanced operating systems (OS), and multimedia, such as audio and video coding and decoding. The ARM11 microarchitecture forms the basis of a new range of ARM11 CPU products, and builds upon the success of the established ARM9E™ and ARM10E™ families of cores.

“System developers demand continual innovation to enable the creation of world class digital products,” said John Rayfield, director of R&D, ARM. “The ARM11 microarchitecture is the foundation of our next generation of CPU cores, and delivers new levels of performance and efficiency for leading-edge wireless and consumer devices.”


The ARM11 microarchitecture is particularly suited to next-generation wireless and consumer devices, where high levels of system performance and low-power consumption are required. These include 2.5G and 3G mobile phone handsets, PDAs and multimedia wireless devices, home consumer applications such as imaging and digital camera applications. The microarchitecture is also designed to meet the needs of home gateway and network infrastructure equipment including voice over IP and broadband modems.

Technical details

The new ARM11 microarchitecture implements the ARMv6 instruction set architecture that includes the Thumb® extensions for code density, Jazelle™ technology for Java™ acceleration, ARM DSP extensions, and SIMD (Single Instruction Multiple Data) media processing extensions.

High performance is delivered using an 8-stage integer pipeline, static and dynamic branch prediction, and separate load-store and arithmetic pipelines to maximize instruction throughput. The ARM11 microarchitecture will deliver 350 to 500+ MHz worst case on 0.13u foundry processes, and over 1 GHz on next-generation 0.1µm processes. The ARM11 microarchitecture achieves optimum power efficiency single-issue operation with out-of-order completion to minimize gate count, consuming less than 0.4 mW/MHz on 0.13u foundry processes.

Multimedia performance is accelerated through the enhanced integer pipeline, new SIMD media instructions, high-performance 64-bit memory system, and hardware support for unaligned data access. Real-time performance is enhanced by using vectored interrupts, and low-interrupt-latency operating modes which, together with ARMv6 architecture enhancements, reduce interrupt handling overhead by 70 percent.

The new ARM11 microarchitecture also provides considerably improved operating system performance by use of physically addressed caches, and new ARMv6 architecture instructions that accelerate context switching. The ARM11 microarchitecture was developed in close consultation with leading operating system vendors and supports the WindowsCE, Symbian OS, Palm OS, and Linux operating systems.


The first CPU using the ARM11 microarchitecture will be publicly announced and released to licensees in Q4 2002.

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